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Journal of Graphics ›› 2026, Vol. 47 ›› Issue (4): 820-833.DOI: 10.11996/JG.j.2095-302X.2026040820

• Digital Design and Manufacture • Previous Articles     Next Articles

Parallel reduction and context-sensitive incremental update method for large-scale wiring harness topology

LI Kai, LIU Shaohua(), HE Zihao, LIU Kangfan, ZHOU Silong   

  1. School of Electronic Engineering, Beijing University of Posts and Telecommunications, Beijing 100876, China
  • Received:2026-01-20 Accepted:2026-05-11 Online:2026-08-31 Published:2026-08-31
  • Contact: LIU Shaohua
  • Supported by:
    National Natural Science Foundation of China(91938301)

Abstract:

The evolution of automotive electrical/electronic architectures increases the design complexity of wiring harness systems and creates bottlenecks in validation efficiency. Traditional graph traversal algorithms also face the challenges of high computational overhead and the lack of real-time feedback in large-scale harness routing and frequent local modifications. To address these challenges, an efficient computing framework based on Reserved Graph Grammar (RGG) was proposed. This framework utilized the two-layer node structure of RGG to establish a wiring harness topology model and proposed a “global topology collapse” strategy. By defining parallel reduction rules, the physical graph was efficiently transformed into a logical connection graph, reducing the algorithmic complexity from O(N2) to O(N). Experimental results showed that in the static routing scenario, this algorithm achieved a speedup ratio of 30.89 times in a 32-thread environment, with a parallel efficiency of 96.5%. Compared with the Contraction Hierarchies (CH) static acceleration algorithm, RGG reduced memory usage by approximately 50% and supported incremental updating. For dynamic design changes, a context-sensitive incremental update mechanism was introduced. In the scenarios of attribute update and topology modification, the performance advantage of incremental update became more significant as the wiring harness scale increased: when the number of nodes increased from 100 to 5 000, the speedup ratio of attribute update increased from 543 times to 4.1×104 times, and the speedup ratio of topology update increased from 3.8 times to 2.2×102 times. Compared with the Ramalingam dynamic shortest path algorithm, RGG provided more stable update time and supported topology modification. Additionally, correctness verification showed that the results of this algorithm were completely consistent with those of the traditional Dijkstra algorithm (MAE=0, R2=1.0), ensuring the complete retention of physical attributes. A low-level engine with both high fidelity and real-time responsiveness was thereby provided for the analysis of ultra-large-scale wiring harnesses.

Key words: reserved graph grammar, topological collapse, parallel reduction, context-sensitive, incremental updating

CLC Number: